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Alif Semiconductor /AE512F80F55D5AS_CM55_HP_View /LPUART /UART_LCR_EXT

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Interpret as UART_LCR_EXT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DLS_E)DLS_E 0 (Val_0x0)ADDR_MATCH 0 (Val_0x0)SEND_ADDR 0 (Val_0x0)TRANSMIT_MODE

TRANSMIT_MODE=Val_0x0, ADDR_MATCH=Val_0x0, SEND_ADDR=Val_0x0

Description

Line Extended Control Register

Fields

DLS_E

Extension for DLS This bit is used to enable 9-bit data for transmit and receive transfers.
ADDR_MATCH

This bit is used to enable the address match feature during Receive mode. This bit is applicable only when UART_LCR_EXT[DLS_E] is set to 1.

0 (Val_0x0): Normal mode. The UART will start to receive the data and 9-bit character will be formed and written into the receive Rx FIFO. Then read the data and differentiate address and data.

1 (Val_0x1): Address match mode. The UART will wait until the incoming character with 9^th bit set to 1 and further checks to see if the address matches with what is programmed in UART_RAR register. If match is found, then sub-sequent characters will be treated as valid data and UART starts receiving data.
SEND_ADDR

This bit is used as a control knob to determine when to send the address during Transmit mode. This bit is auto-cleared, after sending out the address character. This field is applicable only when UART_LCR_EXT[DLS_E] bit is set to 1 and UART_LCR_EXT[TRANSMIT_MODE] is set to 0.

0 (Val_0x0): 9-bit character will be transmitted with 9^th bit set to 0 and the remaining 8-bits will be taken from the Tx FIFO which is programmed through 8-bit wide UART_THR/UART_STHR registers.

1 (Val_0x1): 9-bit character will be transmitted with 9^th bit set to 1 and the remaining 8-bits will match to what is being programmed in UART_TAR register.
TRANSMIT_MODE

This bit is used to control the type of Transmit mode during 9-bit data transfers. Address: 9^th bit set to 1; Data: 9^th bit set to 0. Note: The UART_TAR[TAR] field is not applicable in this mode of operation.

0 (Val_0x0): In this mode of operation, UART_THR[THR] field and from UART_STHR0[STHRN] to UART_STHR15[STHR15] fields are 8-bit wide. Program the address into UART_TAR[TAR] field and data into the UART_THR/UART_STHR registers. The UART_LCR_EXT[SEND_ADDR] bit is used as a control knob to indicate the UART on when to send the address.

1 (Val_0x1): In this mode of operation, UART_THR[THR] field and from UART_STHR0[STHRN] to UART_STHR15[STHR15] fields are 9-bit wide.

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data